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To attain business silicon and design wins for the following era microprocessors by December 2023, the federal government of India on Wednesday introduced the launch of Digital India RISC-V (DIR-V) program. RISC-V is a free and open ISA enabling a brand new period of processor innovation by means of open commonplace collaboration.
The federal government initiative is pegged to be one other concrete step in the direction of realizing the ambition of self-reliance in the direction of “Atmanirbhar Bharat”.
Whereas setting the aggressive milestones for business silicon of SHAKTI & VEGA and their design wins by December 2023, Minister of State for Electronics & Data Expertise and Talent Improvement & Entrepreneurship Rajeev Chandrasekhar talked about that DIR-V will see partnerships between Startups, Academia & Multinationals, to make India not solely a RISC-V Expertise Hub for the World but additionally provider of RISC-V SoC (System on Chips) for Servers, Cellular units, Automotive, IoT & Microcontrollers throughout the globe.
Whereas talking with the media, Chandrasekhar reminisced his early days as x-86 processor chip designer at Intel and talked about that many new processor architectures have gone by means of an preliminary interval of ferment characterised by waves of improvements. In some unspecified time in the future, nevertheless, all of them settled on a dominant design.
ARM and x-86 are two such instruction set architectures- considered one of which is licensed and different is bought, the place trade consolidated in earlier a long time.
Nonetheless, RISC-V has emerged as a powerful various to them in final decade, having no licensing encumbrances, enabling its adoption by every one in semiconductor trade, at totally different complexity ranges for numerous design functions,
Difficult the established order, RISC-V Instruction Set Structure (ISA)
The Ministry of Electronics and IT (MeitY) can be planning to affix the RISC-V Worldwide as Premiere Board Member to collaborate, contribute and advocate India’s experience with different world RISC-V leaders.
Professor V. Kamakoti, Director, IIT Madras would be the Chief Architect and S. Krishnakumar Rao as Program Supervisor of DIR-V Program. Minister Chandrasen additionally unveiled the Blueprint of the roadmap of design & implementation of the DIR-V Program with – SHAKTI Processor by IIT Madras and VEGA Processor by C-DAC together with the strategic Roadmap for India’s Semiconductor Design & Innovation to catalyze the semiconductor ecosystem within the nation.
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