HONG KONG SAR – Media OutReach Newswire – 31 August 2026 – The following era of microelectronics depends on enhancements in transistor switching efficiency to advance computing energy. Nevertheless, standard semiconductor know-how has hit the bodily “Boltzmann restrict”, which restricts the power effectivity of conventional transistors. A analysis workforce at The Hong Kong Polytechnic College (PolyU) has engineered a novel tunnelling field-effect transistor (TFET) utilising 2D nanomaterials. The breakthrough can provide the basics for energy-efficient computing and next-generation AI chips.
Prof. Jianhua Hao (proper), Dr. Zehan Wu, Analysis Assistant Professor of Division of Physics and Supplies at PolyU and the primary writer of the Analysis Article in Science (left), and the analysis workforce, fabricated ultra-thin heterostructure of 2D bismuth and indium selenide layers utilizing pulsed laser deposition.
The analysis was led by Prof. Jianhua HAO, Head of the Division of Physics and Supplies and Chair Professor of Supplies Physics and Units at PolyU, in collaboration with the Nationwide College of Singapore, The Hong Kong College of Science and Know-how, Peking College, and the Singapore College of Know-how and Design. The findings have been printed within the prestigious scientific journal Science.
Standard transistors depend on thermionic emission {of electrical} expenses, which requires a minimal gating voltage of 60 millivolts (mV). Nevertheless, the “Boltzmann restrict” makes subthreshold swing values under 60 mV decade⁻¹ at room temperature bodily unimaginable, limiting progress in high-performance electronics.
Prof. Hao stated, “By adopting quantum tunnelling, our TFET breaks by way of this boundary, paving the way in which for ultra-low-power, high-performance built-in circuits important for rising AI chips and superior semiconductor functions.”
Prof. Hao’s workforce created ultra-thin heterostructure of 2D bismuth and indium selenide alternating layers utilizing pulsed laser deposition. By exercising exact management over the layer construction, the usually semi-metallic bismuth transforms right into a semiconductor in 2D type, permitting cost carriers to tunnel effectively into indium selenide by way of quantum tunnelling mechanism.
The ensuing TFET achieved SS values nicely under the 60 mV decade⁻¹ restrict. Working at room temperature on silicon substrates, the machine required a gate-voltage vary of solely 160 mV—far decrease than the 800 mV initially required.
The machine resolved a problem in experimental TFETs by delivering a excessive output present alongside an exceptionally excessive ON/OFF present ratio, which helps drive a number of downstream logic gates and diminish circuit-delay.
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